Chapter2(STA Concepts ) of Static Timing Analysis for Nanometer Designs

上一篇 / 下一篇  2018-01-30 10:38:55 / 个人分类:STA

1. What is a logic-1 or a logic-0?
    (1) In a CMOS cell, two values VIHmin and VILmax define the limits. That is, any voltage value above VIHmin is considered as a logic-1 and any voltage value below VILmax is considered as a logic-0.

2. What's the inputs and output capacitance?
    (1) Output Cap: If a cell output pin drives multiple fanout cells, the total capacitance on the output pin of the cell is:
          1) the sum of all the input capacitances of the cells that it is driving             
          2) the sum of the capacitance of all the wire segments that comprise the net
          3) the output capacitance of the driving cell(There can also be an output pin capacitance though most CMOS logic cells do not include the pin capacitance for the output pins.)
    (2) Input Cap:Note that in a CMOS cell, the inputs to the cell present a capacitive load only.

3. What's defined how fast the transition?
    (1) When the CMOS cell switches state, the speed of the switching is governed by how fast the capacitance on the output net can be charged or discharged.
    (2) The charging and discharging path resistances are a major factor in determining the speed of the CMOS cell.

4. What's the drive capacity of the cell?
    (1)The inverse of the pull-up resistance is called the output high drive of the cell. The larger the output pull-up structure, the smaller the pull-up resistance and the larger the output high drive of the cell.
    (2) The same concept for the pull-up structure can be applied for the pull-down structure which determines the resistance of the pull-down path and output low drive.
    (3) In general, the cells are designed to have similar drive strengths (both large or both small) for pull-up and pull-down structures.
    (4) The output drive determines the maximum capacitive load that can be driven.The maximum capacitive load determines the maximum number of fanouts, that is, how many other cells it can drive.

5. What's RC time constant and the transition between levels?
        (1) 1-> 0 transition
         V = Vdd * [1 - e -t/(Rdh * Cload)]
         The voltage waveform. for this rise is shown in Figure 2-8(b). The product (Rdh * Cload) is called the RC time constant - typically this is also related tothe transition time of the output.
        (2) 0->1 transition
          V = Vdd * e-t/(Rdl * Cload)
        (3) In a CMOS cell, the output charging and discharging waveforms do not appear like the RC charging and discharging waveforms of Figure 2-8 since the PMOS pull-up and the NMOS pull-down transistors are both on simultaneously for a brief amount of time

6. How to calculate  the propagation delay?
       From input 50% transition time to output 50% transition time.
       input_threshold_pct_fall : 50.0;
       input_threshold_pct_rise : 50.0;
       output_threshold_pct_fall : 50.0;
       output_threshold_pct_rise : 50.0;

7. Slew of a waveform(Transition time)?
    A slew rate is defined as a rate of change;
    The slew is typically measured in terms of the transition time which takes for a signal to transition between two specific levels.
    # Falling edge thresholds:
    slew_lower_threshold_pct_fall : 30.0;
    slew_upper_threshold_pct_fall : 70.0;
    # Rising edge thresholds:
    slew_lower_threshold_pct_rise : 30.0;
    slew_upper_threshold_pct_rise : 70.0;

8. Slow between signals(clock latency and skew)
    Skew is the difference in timing between two or more signals, maybe data, clock or both. if a clock tree has 500 end points and has a skew of 50ps, it means that the difference in latency between the longest path and the shortest clock path is 50ps.
     Clock latency is the total time it takes from the clock source to an end point.
     Clock skew is the difference in arrival times at the end points of the clock tree.
     An ideal clock tree is one where the clock source is assumed to have an infinite drive, that is, the clock can drive infinite sources with no delay.

9. Clock uncertainty(clock skew + clock period jitter + margins(before CTS))


    The set_clock_uncertainty specifies a window within which a clock edge can occur. The uncertainty in the timing of the clock edge is to account for several factors such as clock period jitter and additional margins used for timing verification.
    One can specify different clock uncertainties for setup checks and for hold
checks. The hold checks do not require the clock jitter to be included in the
uncertainty
and thus a smaller value of clock uncertainty is generally specified
for hold.

10 . Three kinds of Timing Arcs

    (1) The timing arc is positive unate if a rising transition on an input causes the output to rise (or not to change) and a falling transition on an input causes the output to fall (or not to change)
    (2) A negative unate timing arc is one where a rising transition on an input
causes the output to have a falling transition (or not to change) and a falling transition on an input causes the output to have a rising transition (or not to change).
    (3) In a non-unate timing arc, the output transition cannot be determined solely from the direction of change of an input but also depends upon the state of the other inputs.


11. Min and Max Timing Paths

    (1) A max path between two end points is the path with the largest delay (also referred to as the longest path).
    (2) A min path is the path with the smallest delay (also referred to as the shortest path).
    (3) Note that the longest and shortest refer to the cumulative delay of the path, not to the number of cells in the path.
    (4) A max path is often called a late path, while a min path is often called an early path.

12. Launch and Capture
     Notice that the launch and capture terminology are always with reference to a flip-flop to flip-flop path
 
13. Clock Domains
     A clock typically feeds a number of flip-flops. The set of flip-flops being fed
by one clock is called its clock domain

14. Whether the clock domains are related or independent of each other?

     (1) whether there are any data paths that start from one clock domain and end in the other clock domain. If there are no such paths, we can safely say that the two clock domains are independent of each other.
    (2) If indeed there are data paths that cross between clock domains a decision has to be made as to whether the paths are real or not.
    (3) If synchronizer is added between two clock domain,it is not a real timing path since the data is not constrained to propagate through the synchronizer logic in one clock cycle.

15. What is the reason to discuss paths between clock domains?   
    Identifying which clock domain crossings are real and which clock crossings are not real is an important part of the timing verification effort. This enables the designer to focus on validating only the real timing paths.


16. Operating Conditions
     There are three kinds of manufacturing process models that are provided
by the semiconductor foundry for digital designs: slow processmodels, typical
process models, and fast process models.
     An operating condition is defined as a combination of Process, Voltage
and Temperature (PVT).
     Process is process corner, it's ss/tt/ff, not the 45nm/18nm process.
     Process vs delay: (Slow is best, Typ is Nom, Fast is Worst)
     Voltage vs delay:(Min is best, Nom is Nom, Fast is Worst)
     Temperature vs delay:(Min is best, Nom is Nom, Max is Worst )

17. Three standard operating conditions

     (1)WCS (Worst-Case Slow): Process is slow, temperature is highest (say 125C) and voltage is lowest
     (2)TYP (Typical): Process is typical, temperature is nominal (say 25C) and voltage is nominal (say 1.2V).
     (3)BCF (Best-Case Fast): Process is fast, temperature is lowest (say -40C) and voltage is highest (say nominal 1.2V plus 10%).

18. What's temperature inversion?
    The delays at low temperatures are not always smaller than the delays at higher temperatures. This is because the device threshold voltage (Vt) margin with respect to the power supply is reduced for nanometer technologies. In such cases, at low power supply, the delay of a lightly loaded cell is higher at low temperatures than at high temperatures. This is especially true of high Vt (higher threshold, larger delay) or even standard Vt (regular threshold, lower delay) cells. This anomalous behavior. of delays increasing at lower temperatures is called temperature inversion.

19. power analysis operating condition:
     (1) ML (Maximal Leakage): Process is fast, temperature is highest (say
125C) and the voltage is also the highest (say 1.2V plus 10%).
     (2) TL (Typical Leakage): Process is typical, temperature is highest
(say 125C) and the voltage is nominal (say 1.2V).



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